S. Minoret: search on Z-Library

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1

High-performance silver-dielectric interference filters for RGBIR imaging

Frey, Laurent, Masarotto, Lilian, El Melhaoui, Loubna, Verrun, Sophie, Minoret, Stéphane, Rodriguez, Guillaume, André, Agathe, Ritton, Frédéric, Parrein, Pascale

Journal:

Year:

2018

Language:

english

File:

PDF, 1.64 MB

english, 2018

2

Investigations of titanium nitride as metal gate material, elaborated by metal organic atomic layer deposition using TDMAT and NH3

F. Fillot, T. Morel, S. Minoret, I. Matko, S. Maîtrejean, B. Guillaumot, B. Chenevier, T. Billon

Journal:

Microelectronic Engineering

Year:

2005

Language:

english

File:

PDF, 196 KB

english, 2005

3

Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 “high k” and 2 metal deposition techniques

V. Cosnier, P. Besson, V. Loup, L. Vandroux, S. Minoret, M. Cassé, X. Garros, J-M. Pedini, S. Lhostis, K. Dabertrand, C. Morin, C. Wiemer, M. Perego, M. Fanciulli

Journal:

Microelectronic Engineering

Year:

2007

Language:

english

File:

PDF, 582 KB

english, 2007

4

Comparative study of non-polar switching behaviors of NiO- and HfO2-based oxide resistive-RAMs

V. Jousseaume, A. Fantini, J.F. Nodin, C. Guedj, A. Persico, J. Buckley, S. Tirano, P. Lorenzi, R. Vignon, H. Feldis, S. Minoret, H. Grampeix, A. Roule, S. Favier, E. Martinez, P. Calka, N. Rochat, G.

Journal:

Solid-State Electronics

Year:

2011

Language:

english

File:

PDF, 1.28 MB

english, 2011

5

[IEEE 2009 11th Electronics Packaging Technology Conference (EPTC) - Singapore, Singapore (2009.12.9-2009.12.11)] 2009 11th Electronics Packaging Technology Conference - Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

Pares, G., Minoret, S., Lugand, J F., Huet, S., Lapras, V., Anciant, R., Henry, D., Sillon, N., Dunne, B.

Year:

2009

Language:

english

File:

PDF, 848 KB

english, 2009

6

CVD Growth and Passivation of W and TiN Nanocrystals for Non-volatile Memory Applications

Gay, Guillaume, Belhachemi, Djamel, Colonna, Jean-Philippe, Minoret, Stéphane, Beaurain, Arnaud, Pelissier, Bernard, Roure, Marie-Christine, Lafond, Dominique, Jalaguier, Eric, Molas, Gabriel, Baron,

Journal:

MRS Proceedings

Year:

2010

Language:

english

File:

PDF, 36.75 MB

english, 2010

7

Metallic nano-crystals for flash memories

J. Dufourcq, P. Mur, M.J. Gordon, S. Minoret, R. Coppard, T. Baron

Journal:

Materials Science and Engineering: C

Year:

2007

Language:

english

File:

PDF, 1.14 MB

english, 2007

8

Properties of innovative resistive memories studied by X-ray and UV photoemission

E. Martinez, C. Guedj, P. Calka, S. Minoret, J. Buckley, Y. Bernard, V. Jousseaume

Journal:

Surface and Interface Analysis

Year:

2010

Language:

english

File:

PDF, 140 KB

english, 2010

9

Origin of resistivity change in NiO thin films studied by hard x-ray photoelectron spectroscopy

Calka, P., Martinez, E., Lafond, D., Minoret, S., Tirano, S., Detlefs, B., Roy, J., Zegenhagen, J., Guedj, C.

Journal:

Journal of Applied Physics

Year:

2011

Language:

english

File:

PDF, 1.64 MB

english, 2011

10

[IEEE Technology (ICICDT) - Kaohsiung, Taiwan (2011.05.2-2011.05.4)] 2011 IEEE International Conference on IC Design & Technology - Through Silicon Via technology using tungsten metallization

Pares, G., Bresson, N., Minoret, S., Lapras, V., Brianceau, P., Lugand, J. F., Anciant, R., Sillon, N.

Year:

2011

Language:

english

File:

PDF, 1.05 MB

english, 2011

11

[IEEE 2006 International Electron Devices Meeting - San Francisco, CA, USA (2006.12.11-2006.12.13)] 2006 International Electron Devices Meeting - Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width

Andrieu, F., Faynot, O., Garros, X., Lafond, D., Buj-Dufournet, C., Tosti, L., Minoret, S., Vidal, V., Barbe, J.C., Allain, F., Rouchouze, E., Vandroux, L., Cosnier, V., Casse, M., Delaye, V., Carabas

Year:

2006

Language:

english

File:

PDF, 1.01 MB

english, 2006

12

Study of low temperature MOCVD deposition of TiN barrier layer for copper diffusion in high aspect ratio through silicon vias

Djomeni, Larissa, Mourier, Thierry, Minoret, Stéphane, Fadloun, Sabrina, Piallat, Fabien, Burgess, Steve, Price, Andrew, Zhou, Yun, Jones, Christopher, Mathiot, Daniel, Maitrejean, Sylvain

Journal:

Microelectronic Engineering

Year:

2014

Language:

english

File:

PDF, 1.72 MB

english, 2014

13

[IEEE 2009 IEEE International Interconnect Technology Conference - IITC - Sapporo, Japan (2009.06.1-2009.06.3)] 2009 IEEE International Interconnect Technology Conference - Back-end-of-line integration approaches for resistive memories

Jousseaume, V., Buckley, J., Bernard, Y., Gonon, P., Vallee, C., Mougenot, M., Feldis, H., Minoret, S., Chamiot-Maitral, G., Persico, A., Zenasni, A., Gely, M., Barnes, J.P., Martinez, E., Grampeix, H

Year:

2009

Language:

english

File:

PDF, 555 KB

english, 2009

14

[IEEE 2010 IEEE International Memory Workshop - Seoul, Korea (South) (2010.05.16-2010.05.19)] 2010 IEEE International Memory Workshop - Comparative study of non-polar switching behaviors of NiO- and HfO2-based Oxide Resistive-RAMs

Jousseaume, V., Fantini, A., Nodin, J.F., Guedj, C., Persico, A., Buckley, J., Tirano, S., Lorenzi, P., Vignon, R., Feldis, H., Minoret, S., Grampeix, H., Roule, A., Favier, S., Martinez, E., Calka, P

Year:

2010

Language:

english

File:

PDF, 941 KB

english, 2010

15

[IEEE 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2013.05.28-2013.05.31)] 2013 IEEE 63rd Electronic Components and Technology Conference - Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer

Sunohara, Masahiro, Miyairi, Ken, Mori, Kenichi, Murayama, Kei, Charbonnier, Jean, Assous, Myriam, Bally, JeanPhilippe, Mourier, Thierry, Minoret, Stephane, Mercier, Denis, Toffoli, Alain, Allain, Fab

Year:

2013

Language:

english

File:

PDF, 2.09 MB

english, 2013

16

[IEEE 2009 IEEE International SOI Conference - Foster City, CA, USA (2009.10.5-2009.10.8)] 2009 IEEE International SOI Conference - Platinum silicide metallic source & drain process optimization for FDSOI pMOSFETs

Carron, V., Nemouchi, F., Morand, Y., Poiroux, T., Vinet, M., Bernasconi, S., Louveau, O., Lafond, D., Delaye, V., Allain, F., Minoret, S., Vandroux, L., Billon, T.

Year:

2009

Language:

english

File:

PDF, 2.31 MB

english, 2009

17

[IEEE 2013 IEEE International Interconnect Technology Conference - IITC - Kyoto, Japan (2013.06.13-2013.06.15)] 2013 IEEE International Interconnect Technology Conference - IITC - 3D Integration challenges today from technological toolbox to industrial prototypes

Mourier, T., Ribiere, C., Romero, G., Gottardi, M., Allouti, N., Eleouet, R., Roman, A., Magis, T., Minoret, S., Ratin, C., Scevola, D., Dupuy, E., Martin, B., Gabette, L., Marseilhan, D., Enot, T., P

Year:

2013

Language:

english

File:

PDF, 874 KB

english, 2013

18

Passivated TiN nanocrystals/SiN trapping layer for enhanced erasing in nonvolatile memory

Gay, G., Belhachemi, D., Colonna, J. P., Minoret, S., Brianceau, P., Lafond, D., Baron, T., Molas, G., Jalaguier, E., Beaurain, A., Pelissier, B., Vidal, V., De Salvo, B.

Journal:

Applied Physics Letters

Year:

2010

Language:

english

File:

PDF, 1.22 MB

english, 2010

19

[IEEE 2006 International Symposium on VLSI Technology, Systems, and Applications - Hsinchu, Taiwan (2006.4.24-2006.4.24)] 2006 International Symposium on VLSI Technology, Systems, and Applications - Impact of WSix Metal Gate Stoichiometry on Fully Depleted SOI MOSFETs Electrical Properties

Widiez, J., Vinet, M., Guillaumot, B., Garros, X., Minoret, S., Poiroux, T., Weber, O., Thevenod, L., Holliger, P., Previtali, B., Barral, V., Ali Cherif, K., Grosgeorges, P., Toffoli, A., Maitrejean,

Year:

2006

Language:

english

File:

PDF, 2.52 MB

english, 2006

20

Éveil visuel à l’image chez de jeunes enfants cérébrolésés : étude pilote d’un accompagnement pluridisciplinaire pour une intégration multimodale

Fintz, A.-C., Colin, E., Schwartz, D., Vermot-Desroches, J., Peter-Faucher, C., Minoret, C.

Journal:

Motricité Cérébrale : Réadaptation, Neurologie du Développement

Year:

2015

File:

PDF, 1.23 MB

2015

21

[ECS 210th ECS Meeting - Cancun, Mexico (October 29-November 3, 2006)] ECS Transactions - Nickel Selective Etching Studies for Self-Aligned Silicide Process in Ge and SiGe-Based Devices

Carron, Veronique, Ribeiro, Mathilde, Besson, Pascal, Rolland, Guy, Hartmann, Jean-Michel, Loup, Virginie, Minoret, Stephane, Clavelier, Laurent, Leroyer, Cyrille, Billon, Thierry

Year:

2006

Language:

english

File:

PDF, 3.29 MB

english, 2006

22

Analysis of High Aspect Ratio through Silicon via (TSV) Diffusion and Stress Impact Profile during 3D Advanced Integration

Djomeni, L., Mourier, T., Minoret, S., Fadloun, S., Barnes, J.-P., Rouchon, D., Burgess, S., Price, A., Vandroux, L., Mathiot, D.

Journal:

ECS Transactions

Year:

2014

Language:

english

File:

PDF, 562 KB

english, 2014

23

[IEEE 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) - Saratoga Springs, NY, USA (2015.5.3-2015.5.6)] 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) - Through silicon via process characterization by integrated inspection/metrology solutions in visible and infrared domain

Devanciard, Nicolas, Rey, Stephane, Magis, Thomas, Minoret, Stephane, Beitia, Carlos, Alliata, Dario, Marx, David, Bachiraju, Prasad, Hart, Darcy, Thornell, John, Dudley, Russ

Year:

2015

Language:

english

File:

PDF, 2.03 MB

english, 2015

24

Interface chemical characterization of novel W∕HfO[sub 2]∕GeON∕Ge stacks

E. Martinez, O. Renault, L. Clavelier, C. Le Royer, J. Hartmann, V. Loup, S. Minoret, V. Cosnier, Y. Campidelli, J. Zegenhagen, T. Lee

Year:

2007

Language:

english

File:

PDF, 561 KB

english, 2007

25

[IEEE 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) - Singapore (2015.12.2-2015.12.4)] 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) - Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias

Gaillard, F., Mourier, T., Religieux, L., Bouchu, D., Ribiere, C., Minoret, S., Gottardi, M., Romero, G., Mevellec, V., Aumont, C.

Year:

2015

Language:

english

File:

PDF, 1.35 MB

english, 2015

26

Conformal isolation of high-aspect-ratio TSVs using a low-κ dielectric deposited by filament-assisted CVD

Jousseaume, V., Altemus, B., Ribière, C., Minoret, S., Gottardi, M., Ratin, C., Ichiki, K., Mourier, T., Faguet, J.

Journal:

Microelectronic Engineering

Year:

2017

Language:

english

File:

PDF, 1.29 MB

english, 2017

27

Focused ion beam time-of-flight secondary ion mass spectroscopy tomography of through-silicon vias for 3D integration

Barnes, Jean-Paul, Djomeni, Larissa, Minoret, Stéphane, Mourier, Thierry, Fabbri, Jean-Marc, Audoit, Guillaume, Fadloun, Sabrina

Journal:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures

Year:

2016

Language:

english

File:

PDF, 1.14 MB

english, 2016

28

[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly

Charbonnier, Jean, Assous, Myriam, Mourier, Thierry, Ribiere, Celine, Minoret, Stephane, Verrun, Sophie, Tissier, Pierre, Coquand, Remi, Bicer, Mehmet, Allain, Fabienne, Franiatte, Remi, Pares, Gabrie

Year:

2019

File:

PDF, 937 KB

2019